The present invention relates in general to power factor correction (PFC) circuitry and, more specifically, how to reduce cost and improve converter specifications when interleaving PFCs.
Regulations in various countries have mandated the need for a high power factor in AC/DC converters and other loads that may affect the line power factor. As known in the art, a high power factor condition exists when the alternating current (AC) load is resistive, the current and voltage are in phase and the power factor is 100%. In the industry, one of many standard approaches to obtain a higher power factor condition is to control converter input current using a boost topology. Many basic details relative power factor correction may be found in various textbooks, such as Chapter 15 of xe2x80x9cSwitching Power Supply Designxe2x80x9d Second Edition published by McGraw Hill and Authored by Abraham I Pressman.
One typical control integrated circuit (IC) utilized in the industry is a standardized chip designated as a 2818, a version of which is available from Texas Instruments, Inc. (TI) as a UCC2818. Application notes, entitled xe2x80x9cBiCMOS POWER FACTOR PREREGULATOR,xe2x80x9d are available from TI for a family of ICs including the 2818 IC. The 2818 chip implements a technique known as average current mode control. As the name implies, this technique controls the average input current.
Although the average input current may be sensed with a single resistor placed in the return to the rectified source, a considerable amount of power is dissipated (and wasted) in this approach. Thus, most average current PFC circuits use two current transformers (CTs) for sensing, summing and averaging the current in both a switch leg and diode or non-switch leg of the PFC circuit. CTs, however, add size and cost to a PFC circuit.
One approach to reducing size and weight is to use a single CT in the switch leg of the PFC circuit to detect only the peak switch current. In the industry, this approach is referred to as current mode control (CMC). More detail on an IC that can be used to provide such a peak current controller may be found in an application note from TI, entitled xe2x80x9cBiCMOS Low Power Current Mode PWM Controller.xe2x80x9d It is well known in the industry that the CMC approach is unstable when the switch duty cycle exceeds 50%. The CMC can be made stable by implementing a technique known as slope compensation. This technique is implemented by adding a slope to the current ramp, as set forth in a July 1996 IEEE (APEC) article by C. Canesin, entitled xe2x80x9cAnalysis and Design of Constant Frequency Peak Current Controlled High Power Factor Rectifier with Slope Compensationxe2x80x9d on pp 807-813. A difficulty of such an approach is that CMC does not perform as well as average current mode in PFC applications. More detail on this situation may be obtained from a paper by R. Redl, entitled xe2x80x9cReducing Distortion in Peak-Current-Controlled Boost Power-Factor Correctors,xe2x80x9d IEEE (APEC) 1994, pp. 576-583.
It is further known in the art that interleaving controllers (paralleling) allows the use of smaller components or, alternatively, components that are not available with high current ratings. Further, electronic emission interference (emi) signals are reduced when using interleaved controllers due to the lower amount of ripple. However, current sharing is not guaranteed when using two average current controllers, as set forth in a paper by L. Balogh, entitled xe2x80x9cPower Factor Correction with Interleaved Boost Converters in Continuous-Inductor-Current Mode,xe2x80x9d IEEE (APEC) 1993, pp. 168-174. When the current is not equally shared between multiple units, the different peak currents can increase the emi and increase design size and cost over what would occur in an optimized interleaved unit. The size and cost increase is generally due to a safety factor being built into the controller design to accommodate unbalanced currents in the interleaved converters. Thus, interleaved PFC units typically are designed using CMC with slope compensation as set forth in a paper by R. Giral, entitled xe2x80x9cInterleaved Converters Operation Based on CMCxe2x80x9d IEEE (APEC), pp. 643-652.
It has been found that average current mode PFC controllers obtain better power factor than do peak (CMC) controllers. The measurements used in the industry are total harmonic distortion and power factor. The total harmonic distortion in an average current mode PFC is typically improved over a comparable CMC unit.
It would thus be desirable to be able to use interleaved controllers that equally share the load current for low emi and allow the use of low current, lower cost components and lower weight components while obtaining the lower total harmonic distortion available from an average current mode PFC controller.
The present invention comprises providing peak or CMC control to a master and one or more slave controllers from a switch leg control transformer (CT). Thus, the input current is substantially equally divided between controllers. A further or extra CT, situated in the non-switched leg of only the master controller, is used in combination with the switch leg CT whereby the average current may be determined and used in a single average current controller. The difference between a reference current logically obtained from the average current controller and the actual current commanded by the CMC controller is compared to create a switch leg control signal that may be used by the slave CMC controllers to obtain high power factor.